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5 kv, 6 - channel, spisolator digital isolator for spi with delay clock data sheet adum4150 features supports up to 40 mhz spi clock speed in delay clock mode supports up to 17 mhz spi clock speed in 4 - wire mode 4 high speed, low propagation delay , spi signal isolation channels 2 data channels at 250 kbps delayed c ompensation clock line 20 - lead s oic_ic wi th 8.3 mm creepage high temperature operation: 125 c high common - mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition per ul 1577 5000 v rms for 1 minute soic long package c sa component acceptance notice 5a vde certificate of conformity din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 84 9 v peak applications industrial programmable logic controllers ( plc ) sensor i solation functional block dia gram figure 1. general descript ion the adum415 0 1 is a 6 - channel , spisolator? digital isolator optimized for isolated serial peripheral interfaces (spis) . based on the analog devices, inc., i coupler? chip scale transformer technology, the low propagation delay in the clk, mo/si, mi/so, and ss spi bus signals supports spi clock rates of up to 17 mhz . these channels operate wi th 13 ns propagation delay and 1 ns jitter to optimize timing for spi. the adum4150 isolator also provides two additional independent lo w data rate isolation channels , one channel in each direction. data in the slow channels is sampled and serialized for a 250 kbps data rate with 2.5 s of jitter . the adum4150 support s a delay clock output on the master side of the device . this output can be used with an additional clocked port on the master to support 40 mhz clock performance . see the delay clock section for more information. table 1 . related products product description adum3150 3.75 kv, high speed, clock delayed spisolator adum3151 / adum3152 / adum3153 3.75 kv, multichannel spi solator adum3154 3.75 kv, multiple slave spi solator adum4151 / adum4152 / adum4153 5 kv, multichannel spi solator adum4154 5 kv, multiple slave spi solator 1 protected by u.s. patents 5,952,849; 6,873,065; 6,262,600 ; and 7,075,329. other patents are pending. encode clk delay control block decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss v ia v ob v dd2 gnd 2 sclk si so sss v oa v ib 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 dclk gnd 1 nic gnd 2 9 10 12 11 adum4150 control block 12371-001 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwi se under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com
adum4150 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 5 electrical characteristics mixed 5 v/3.3 v operation ........ 7 electrical characteristics mixed 3.3 v/5 v operation ........ 9 package characteristics ............................................................. 11 regulatory information ............................................................. 11 insulation and safety related specifications .......................... 11 din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 insulation characteristics ............................................................................ 12 recommended operating conditions .................................... 12 absolute maximum ratings ......................................................... 13 esd caution ................................................................................ 13 pin configuration and function descriptions ........................... 14 typical performance characteristics ........................................... 15 applications information .............................................................. 16 introduction ................................................................................ 16 printed circuit board (pcb) layout ....................................... 17 propagation delay related parameters ................................... 18 dc correctness and magnetic field immunity ..................... 18 power consumption .................................................................. 19 insulation lifetime ..................................................................... 19 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 3 / 15 rev. 0 to rev. a changes to features section and table 1 ...................................... 1 change s to supply current parameter, table 3 ............................ 4 changes to supply current parameter, table 5 ............................ 6 changes to supply current parameter, table 7 ............................ 8 changes to supply curre nt parameter, table 9 .......................... 10 changes to table 11 ........................................................................ 11 changes to table 13 ........................................................................ 12 changes to high speed channels section .................................. 16 10 /14 revision 0 : initial version rev. a | page 2 of 21
data sheet adum4150 specifications electrical character istics 5 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 5 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v, and ? 40c t a + 1 2 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 2 . switching spec i fications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 0 17 mhz data rate fast (mo, so) dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 2 4 12 1 3 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 2 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 21 2 4 21 2 4 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk 3 da ta rate 40 40 mhz propagation delay t phl , t plh 50 35 ns t pmclk + t pso + 3 ns pulse width distortion pwd 3 3 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit clock delay error dclk err 0 4.5 12 1 5.5 12 ns t pdclk ? (t pmclk + t pso ) jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 4 minimum input skew 5 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to gua rantee that mss reaches the output ahead of another fast signal, set up mss prior to the compe ting signal by different times depending on speed grade. 3 t pmclk is the propagation delay of the mclk signal from side 1 to side 2. t pso is the propagation delay of the so signal from side 2 to side 1. t pdclk is the difference between the dclk signal and the round trip propagation delay. 4 v ix = v ia or v ib . 5 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 3 of 21
adum4150 data sheet table 3 . for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 5 8. 5 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz i dd2 6. 5 11 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 15 23 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz i dd2 13.5 21 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz dc specifications mclk , mss , mo, so, v ia , v ib input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , dclk output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current per high speed channel dynamic input i ddi(d) 0.0 8 0 ma/mbps dynamic output i ddo(d) 0.0 4 6 ma/mbps supply current for all low speed channels quiescent si d e 1 current i dd1 (q) 4. 4 ma quiescent side 2 current i dd2 ( q) 6.1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v , t ransient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins . 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits . the common - mode vol tage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 4 of 21
data sheet adum4150 electrical character istics 3 .3 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 3. 3 v. minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v, and ?40 c t a + 1 2 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 4 . switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 8.3 12.5 mhz data rate fast (mo, so) dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 30 20 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 3 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 30 30 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk 3 data rate 40 40 mhz propagation delay t phl , t plh 60 40 ns t pmclk + t pso + 3 ns pulse width distortion pwd 3 3 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit clock delay error dclk err ? 4 + 2.4 + 9 ? 3 + 2.5 + 8 ns t pdclk ? (t pmclk + t pso ) jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 4 minimum input skew 5 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 th e mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to gua rantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 t pmclk is the propagation delay of the mclk signal from side 1 to side 2. t pso is the propagation delay of the so signal from side 2 to side 1. t pdclk is the di fference between the dclk signal and the round trip propagation delay. 4 v ix = v ia or v ib . 5 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end applicatio n, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 5 of 21
adum4150 data sheet table 5 . for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 3.5 6 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz i dd2 4.9 8 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 9.5 20 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz i dd2 8 16 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz dc specifications mclk , mss , mo, so, v ia , v ib input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , dclk output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current per high speed channel dynamic input i ddi(d) 0.0 86 ma/mbps dynamic output i ddo(d) 0.0 1 9 ma/mbps supply current for all low speed channels quiescent si d e 1 current i dd1(q) 2.9 ma quiescent side 2 current i dd2 ( q) 4.6 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v , t ransient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins. 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limi ts . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 6 of 21
data sheet adum4150 electrical character istics mixed 5 v/3 .3 v operation all typical specifications are at t a = 25c, v dd1 = 5 v, and v dd2 = 3.3 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v, and ?40 c t a + 1 2 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 6 . switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 9.2 15.6 mhz data rate fast ( mo, so ) dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 2 7 1 6 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 2 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 2 6 26 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk 3 data rate 40 40 mhz propagation delay t phl , t plh 50 3 5 ns t pmclk + t pso + 3 ns pulse width distortion pwd 3 3 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit clock delay error dclk err ? 5 0 + 7 ? 5 + 1.2 + 9 ns t pdclk ? (t pmclk + t pso ) jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 4 minimum input skew 5 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the i solation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to gua rantee that mss reaches the output ahead of another fast signal , se t up mss prior to the competing signal by different times depending on speed grade. 3 t pmclk is the propagation delay of the mclk signal from side 1 to side 2. t pso is the propagation delay of the so signal from side 2 to side 1. t pdclk is the difference between the dclk signal and the round trip propagation delay. 4 v ix = v ia or v ib . 5 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 7 of 21
adum4150 data sheet table 7 . for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 5.3 8.5 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz i dd2 4.9 8 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 16 23 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz i dd2 10 16 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz dc specifications mclk , mss , mo, so, v ia , v ib input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , dclk output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for all low speed channels quiescent si d e 1 current i dd1(q) 4. 4 ma quiescent side 2 current i dd2 ( q) 4. 6 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v , t ransient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins . 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 8 of 21
data sheet adum4150 el ectrical characteris tics mixed 3 .3 v/ 5 v operation all typical specifications are at t a = 25c, v dd1 = 3. 3 v and v dd2 = 5 v . minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v, and ?40 c t a + 1 2 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherw ise noted. table 8 . switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 9.2 15.6 mhz data rate fast ( mo, so ) dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 2 7 1 6 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 3 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 40 40 mbps within pwd limit propagation delay t phl , t plh 2 6 2 6 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk 3 data rate 40 40 mhz propagation delay t phl , t plh 60 40 ns t pmclk + t pso + 3 ns pulse width distortion pwd 3 3 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit clock delay error dclk err 2 7 13 2 6.8 11 ns t pdclk ? (t pmclk + t pso ) jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 4 minimum input skew 5 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in put s on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to gua rantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 t pmclk is the propagation delay of the mclk signal from side 1 to side 2. t pso is the propagation delay of the so signal from side 2 to side 1. t pdclk is the difference between the dclk signal and the round trip propagation delay. 4 v ix = v ia or v ib . 5 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 9 of 21
adum4150 data sheet table 9 . for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 3.5 6 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz i dd2 6.8 11 ma c l = 0 pf, dr fas t = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 12.5 20 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz i dd2 14 21 ma c l = 0 pf, dr fas t = 17 mhz , dr slow = 0 mhz dc specifications mclk , mss , mo, so, v ia , v ib input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi, si, v oa , v ob , dclk output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for all low speed channels quiescent si d e 1 current i dd1(q) 2. 9 ma quiescent side 2 current i dd2 ( q) 6. 1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v , t ransient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins . 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. a | page 10 of 21
data sheet adum4150 package characterist ics table 10. parameter symbol min typ max unit test conditions /comments resistance (input to output ) 1 r i- o 10 12 capacitance (input to output ) 1 c i - o 1.0 pf f = 1 mhz input capacitanc e 2 c i 4.0 pf ic junction - to - am b ient thermal resistance ja 46 c/w thermocouple located at center of package underside 1 the device is considered a 2 - terminal devi ce: pin 1 throug h pin 10 are shorted together, and pin 11 through pin 20 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory informati on the adum4150 is approved by the organizations listed in table 11. see table 16 and the insulation lifetime s ection for recommended maximum working voltages for specific cross - isolation waveforms and insulation levels. table 11. ul csa vde recognized u nder ul 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din v vde v 0884 -10 (vde v 0884 - 10):2006 -12 2 5000 v rms single protection basic insulation per csa 60950 -1 -07 +a1 +a2 and iec 60950 -1 2nd ed+a1+a2. , 800 v rms (1131 v peak) maximum working voltage 3 reinforced insulation, 84 9 v peak reinforced insulation per csa 60950 -1 - 07+a1+a2 and iec 60950 -1 2 nd ed.+a1+a2, 400 v rms (565 v peak) maximum working voltage reinforced insulation (2mopp) per iec 60601 -1 ed.3.1, 250 v rms (353 v peak) maximum working file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each model is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 10 a ). 2 in accordance with din v vde v 0884 - 10 , each model is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the a sterisk (* ) marked on the component designates din v vde v 0884 - 10 approval. 3 use at working voltages above 400 v ac rms shortens lifetime of the isolator significantly. see table 16 for recommended maximum working voltages under ac and dc conditions. insulation and safet y related specificatio ns table 12. parameter symbol value unit conditions rated dielectric insulation voltage 5000 v rms 1 - minute duration minimum external air gap (clearance) l(i01) 8.3 mm min measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.3 mm min measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 mm min insulation distance through insulation tracking resistance (compar ative tracking index) cti > 400 v din iec 112/vde 0303 part 1 material group ii material group (din vde 0110, 1/89, table 1) rev. a | page 11 of 21
adum4150 data sheet din v vde v 0884 - 10 (vde v 0884 - 10) : 2006 - 12 insulation character istics this isolator is suitable for reinforced electrical isolation only within the safety limit data . maintenance of the safety data is ensured by protective circuits. the asterisk ( * ) marked on packages denotes din v vde v 0884 - 10 approval. table 13. description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input -to - output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 159 2 v peak input -to - output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 1 2 7 4 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 101 9 v peak highest allowable overvoltage v iotm 6000 v peak surge isolation voltage v iosm(test) = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6 25 0 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) case temperature t s 1 50 c safety total dissipated power p s 2.4 w insulation resistance at t s v io = 500 v r s >10 9 figure 2. thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 recommended operatin g conditions table 14. parameter symbol value operating temperature range t a ?40c to +125c supply voltage range 1 v dd1 , v dd2 3.0 v to 5.5 v input signal rise/fall times 1.0 ms 1 s ee the dc correctness and magnetic field immunity section for information on the immunity to external magnetic fields. 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 safe limiting power (w) ambient temperature (c) 12371-002 rev. a | page 12 of 21
data sheet adum4150 rev. a | page 13 of 21 absolute maximum ratings t a = 25c, unless otherwise noted. table 15. parameter rating 1 storage temperature (t st ) range ?65c to +150c ambient operating temperature (t a ) range ?40c to +125c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages (v ia , v ib , mclk, mo, so, mss ) ?0.5 v to v ddx + 0.5 v output voltages (sclk, dclk, sss , mi, si, v oa , v ob ) ?0.5 v to v ddx + 0.5 v average output current per pin 2 ?10 ma to +10 ma common-mode transients 3 ?100 kv/s to +100 kv/s 1 v ddx = v dd1 or v dd2 . 2 see figure 2 for maximum safety rated current values across temperature. 3 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the ab solute maximum ratings may cause latch-up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 16. maximum continuous working voltage 1 parameter value constraint 60 hz ac voltage 400 v rms 20 year lifetime at 0.1% failure rate, zero average voltage dc voltage 1173 v peak limited by the creepage of the package, pollution degree 2, material group ii 2, 3 1 see the insulation lifetime section for details. 2 other pollution degree and material grou p requirements yield a different limit. 3 some system level standards allow components to use the printed wiring board (pwb) creepage values. the supported dc voltage may be higher for those standards. esd caution
adum4150 data sheet pin configuration an d function descripti ons figure 3 . pin configuration table 17. pin function descriptions pin no. mnemonic direction description 1 v dd 1 power input power supply for isolator side 1 . a bypass capacitor from v dd1 to gnd 1 to local ground is required . 2,10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk clock spi clock from the master c ontroller . 4 mo input spi data from the master to the slave mo / si l ine . 5 mi output spi data f rom slave to the m aster mi / so l ine. 6 mss input slave select from the master. this signal uses an active low logic. the slave select pin may require as much as 10 ns setup time from the next clock or data edge, depending on speed grade. 7 v ia input low speed data input a . 8 v ob output low speed data output b . 9 dclk output delayed clock out put. this pin p rovides a delayed copy of the mclk. 11,19 gnd 2 return ground 2. ground reference for isolator side 2. 12 n i c none no internal connection . this pin is not internally connected and serves no function in the adum4150 . 13 v ib input low speed data input b . 14 v oa output low speed data output a . 15 sss output slave select to the s lave. this signal uses an active low logic. 16 so input spi data from the s lave to the m aster mi / so l ine. 17 si output spi data from the m aster to the slave mo / si l ine. 18 sclk output spi clock from the master c ontroller . 20 v dd2 power input power supply for isolator side 2. a bypass capacitor from v dd2 to gnd 2 to local ground is required. table 18. power - off default state truth table (positive logic) 1 v dd1 state v dd2 state side 1 outputs side 2 outputs sss notes unpowered powered z z z outputs on an unpowered side are high impedance within one diode drop of ground powered unpowered z z z outputs on an unpowered side are high impedance within one diode drop of ground 1 z is high impedance. v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 v ia 7 16 15 14 v ob 8 13 dclk 9 12 gnd 1 v dd2 gnd 2 sclk si so sss v oa v ib nic gnd 2 10 11 adum4150 top view (not to scale) notes 1. nic = not internally connected. this pin is not internally connected and serves no function in the adum4150. 12371-003 rev. a | page 14 of 21
data sheet adum4150 typical performance characteristics figure 4. typical dynamic supply current per input channel vs. data rate for 5.0 v and 3 .3 v operation figure 5. typical dynamic supply current per output channel vs. data rate for 5.0 v and 3 .3 v operation figure 6 . typical i dd1 supply current vs. data rate for 5.0 v and 3 .3 v operation figure 7 . typical i dd2 supply current vs. data rate for 5.0 v and 3 .3 v operation figure 8. typical propagation delay vs. ambient temperature for high speed channels without glitch filter (see the high speed channels section for additional information) figure 9. typical propagation delay vs. ambient tempe rature for h igh speed channels w ith glitch filter (see the high speed channels section for additional information) 0 1 2 3 4 5 7 6 0 20 40 60 80 data rate (mbps) 3.3v 5.0v dynamic supply current per input channel (ma) 12371-004 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 20 40 60 80 data rate (mbps) 3.3v 5.0v dynamic supply current per output channel (ma) 12371-005 0 5 10 15 20 25 35 30 0 20 40 60 80 i dd1 supp l y current (ma) dat a r a te (mbps) 3 . 3 v 5 .0v 12371-006 0 5 10 15 20 25 0 20 40 60 80 i dd2 supply current (ma) data rate (mbps) 3.3v 5.0v 12371-007 0 2 4 6 8 10 12 14 16 ?40 10 60 110 propagation delay (ns) ambient temperature (c) 3.3v 5.0v 12371-008 ?40 10 60 110 ambient temperature (c) 3.3v 5.0v 0 5 10 15 20 25 propagation delay (ns) 12371-009 rev. a | page 15 of 21
adum4150 data sheet applications information introduction the adum4150 is part of a family of devices created to optimiz e isolation of spi for speed an d to provide additional low speed c h annels for control and status monitoring functio ns. the isolators are based on d ifferential signaling i coupler technology for enhanced speed and noise immunity. high speed channels the adum4150 has four high speed channels . the first three, clk, mi / so, and mo / si (the slash indicates the connection of the particular input and outpu t , forming a datapath across the isolator that corresponds to a n spi bus signal ) , are optimized for either low propagation delay in the b grade, or high noise immunity in the a grade. the difference between the grades is the addition of a glitch filter to these three channels in the a grade version , which increases propagation delay. the b grade version, with a maximum propagation delay of 1 3 ns , support s a maximum clock rate of 17 mhz in a standard 4 - wire spi . however, because the glitch filter is not present in the b grade version, en sure that spurious glitches of less than 10 n s are not present. glitches of less than 10 n s in the b grade devices can cause the second edge of the glitch to be missed. this pulse condition is seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. it is recommended to use a grade devices in noisy environments. the relationship between the spi signal paths and the pin mnemonic s of the adum4150 and data directions is summarized in table 19. table 19. pin mnemonic correspondence to spi signal path names spi signal path master s ide 1 data direction slave side 2 clk mclk the datapaths are spi mode agnostic. the clk and mo /si spi data paths are optimized fo r propagation delay and channel - to - channel matching. the mi / so spi datapath is optimized fo r propagation delay. the device do es not s ynchronize to the clock channel, so there are no constraints on the clock polarity or the timing with respect to the data line s. to allow compatibility with nonstandard spi interfaces, the mi pin is always active, an d does not tristate when the slave select is not asserted. this precludes tying several mi line s together without adding a tri sate buffer or multiplexor. t he ss (slave select b ar) is typically an active low signal. it can have many different functions in spi and spi like busses. many of thes e functions are edge triggered; therefore, the ss path contains a glitch fi lter in both the a grade and the b grade . the glitch filter prevent s short pulses from propagating to t he output or causing other errors in operation . t he mss signal requires a 10 n s setup time in the b grade prior to the first active clock edge to allow the added propagation time of the glitch filter . low speed data channels the low speed data channels are provided as economical isol ated data paths whe re timing is not critical. the dc value of a ll high and low speed inputs on a given side of the device is sampled simultaneously, packetized , and shifted across an isolation coil. the high spe ed channels are compared for dc accuracy , and the low speed data is transferred to the appropriate low speed outputs. the process is then reversed by reading the inputs on the opposite side of the device , packetizing them , and sending them back for similar processing . the dc correctness data for the high speed channels is handled internally , and the low speed data is clocked to the outputs simultaneously. this bidirectional data shuttling is regulated b y a free running internal clock. because data is sa m pled at discrete times based on this clock, the propagation del ay for a low speed channel is between 0.1 s and 2.6 s depending on where the input data edge changes with respect to the internal sample clock. figure 10 illustrates the beh avior of the low speed channels. ? point a: th e data may change as much as 2. 6 s before it is sampled, then it take s about 0.1 s to propagate to the output. this difference appear s as 2.5 s of uncertainty in the propagation delay time. ? point b: data pulses that are less than the minimum low speed pulse width may not be transmitted at all because they may not be sampled. figure 10 . low speed channel timing input a output a sample clock output clock a b a b 12371-010 rev. a | page 16 of 21
data sheet adum4150 d elay clock the delay clock ( dclk ) function allow s spi data transfers at speeds beyond the limitations usually set by propagation delay. the max imum speed of the clock in a 4 - wire spi application is set by the requirement that data sh ifts out on one clock edge and returning data shifts in on the complementary clock edge. in isolated systems, the delay through the isolator is significant. the first clock edge , tell ing the slave to present its data , must propagate through the isolator. t he sl a ve acts upon the clock edge, and data propagates back through the isolator to the master . the data must arrive back at the master before the complementary clock edge for the data to shift properly into the master. for the example shown in figure 11 , if an isolator has a 50 n s propagation delay, it require s more than 1 00 n s for the response from the slave to arrive back at the master. thi s means that the fastest clock period for the spi bus is 2 00 n s or 5 mhz, and assume s ideal conditions , such as no trace propagation delay or delay in the slave for simplicity. figure 11 . standard spi configuration to avoid this limitation on the spi clock , a second receive buffer can be used as shown in figure 12, together with a clock signal that is delayed to ma tch the data coming back from the slave. the proper delay of the clock was accomplished in the past by sending a copy of the clock back thro ugh a matching isolator channel and using the delayed clock to shift the slave data into a secondary buffer . using an extra channel is costly because it consumes an additional high speed isolator channel. figure 12 . high speed spi using isolation channel delay the adum4150 eliminates the need for the extra high speed channel by implementing a delay circuit on the master side , as shown in figure 13. dclk is trimmed at the production t est to match the round trip propagation delay of each isolator. the dclk signal can be used as if the clock signal had propagated alongside the data from the slave in the scheme outlined previously. figure 13 . high speed spi using precision clock delay this configuration can operate at clock rates of up to 40 mhz. the mi/ so data is shifted into the secondary receive buffer by dclk and then transferred internally by the master to its final destination. the adum4150 does not need to use an extra expensive isolator cha nnel to achieve these data transfer speeds. note that the ss channel is not show n here for clarity. printed circuit board (pcb) layout the adum4150 digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at both the v dd1 and v dd2 supply pins ( see figure 14) . the capacitor value must be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. figure 14 . recommended pcb layout in applications involving high common - mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the pcb layout so that any coupling that does occur equally affects all pins on a given component side. failure to ensure this may cause voltage differentials between pins that exceed the absolute maximum rating s of the device , thereby leading to latch - up or permanent damage. master isolator slave clk mosi miso 12371-0 1 1 master isolator slave clk mosi miso dclk 12371-012 master adum4150 slave clk mosi miso dclk delay 12371-013 bypass < 10mm v dd1 gnd 1 mclk mo mi mss v ia v ob v dd2 gnd 2 sclk si so sss v oa v ib dclk gnd 1 nic gnd 2 adum4150 12371-014 rev. a | page 17 of 21
adum4150 data sheet propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the input - to - output propagation delay time for a high - to - low transition can differ from the propagation delay time of a low - to - high transition . figure 15 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values , and an indication of how accurately the timing of the input signal is preserved. channel - to - channel matching refers to the maximum amount that the propagation delay differs between channels within a single adum4150 component. dc correctness and m agnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is , therefore, either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 .2 s, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed cha nnel to ensure dc correctness at the output. if the low speed decoder receives no pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a high - z state by the watchdog timer circuit . the limitation on the magnetic field immunity of the device is set by the condition in which the induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the followi ng analysis defines such conditions. the adum4150 is examined in a 3 v operating condition because it represents the most suscep tible mode of operation for this product. the pulses at the transformer output have amplitude s greater than 1.5 v. the decoder has a sensing threshold of about 1.0 v, therefore establishing a 0.5 v margin in which induced voltages are tolerated. the voltag e induced across the receiving coil is given by v = ( ? d M dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density. r n is the radius of the n th turn in the receiving coil. n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum4150 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowab le magnetic field is calculated as shown in figure 16. figure 16 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.5 k g auss induces a voltage of 0.25 v at the receiving coil. this voltage is about 50% of the sensing threshold a nd does not cause a faulty output transition. if such an event occurs, with the worst - case polarity, during a transmitted pulse , the interference reduces the received pulse from >1.0 v to 0.75 v. this voltage is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum4150 transformers. figure 17 expresses these allowable current magnitudes as a function of frequency for selected distances. the adum4150 is very insensitive to external fields. only extremely large, high frequency currents very close to the component may potential ly be concern s . for the 1 mhz example noted, placing a 1.2 ka current 5 mm away fro m the adum4150 affects component operation. figure 17 . maximum allowable current for various current to adum4150 spacings note that at combinations of strong magnetic field and high frequency, any loops formed by pcb traces may induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. take care to avoid pcb structures that form loops. input output t plh t phl 50% 50% 12371-015 magnetic field frequency (hz) maximum allowable magnetic flux density (kgauss) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 12371-016 magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 12371-017 rev. a | page 18 of 21
data sheet adum4150 power consumption the supply current at a given channel of the adum4150 isolator is a function of the supply voltage, the data rate of the channel , and the output load of the channel and whether it is a high or low speed channel. the low sp eed channels draw a constant quiescent current caused by the internal ping - pong datapath. the operating frequency is low enough that the capacitive losses caused by the recommended capacitive load are negligible compared to the quiescent current. the expli cit calculation for the data rate is eliminated for simplicity, and the quiescent current for each side of the isolator attributable to the low speed channels can be found in table 3 , table 5 , table 7 , and table 9 for the particular operating voltages. these quiescent currents add to th e high speed current , as shown in the following equations , for the total current for each side of the isolator. dynamic currents are from table 3 and table 5 for the respective voltages. f or s ide 1, the supply current is given by i dd1 = i ddi (d) ( f mclk + f mo + f mss ) + f mi ( i ddo(d) + ((0.5 10 ? 3 ) c l(mi) v dd1 )) + f mclk ( i ddo(d) + ((0.5 10 ? 3 ) c l(dclk) v dd1 )) + i dd1(q) for s ide 2, the supply current is given by i dd2 = i ddi (d) f so + f s c lk ( i ddo(d) + ((0.5 10 ? 3 ) c l(sclk ) v dd2 )) + f si ( i ddo(d) + ((0.5 10 ? 3 ) c l( s i ) v dd2 )) + f ssx ( i ddo(d) + ((0.5 10 ? 3 ) c l(ssx) v dd2 )) + i dd2 (q) where: i ddi(d) , i ddo(d) are the input and output dynamic supply currents per channel (ma/mbps). f x is the logic signal data rate for the specified channel, expressed in units of mbps. c l(x) is the load capacitance of the specified output (pf). v ddx is the supply voltage of the side being evaluated (v). i dd1(q) , i dd2(q) are the specified s ide 1 and s ide 2 quiescent supply currents (ma). figure 4 and figure 5 show the typical dynamic supply current per channel as a function of data rate for an input and unloaded output. figure 6 and figure 7 show the total i dd1 and i dd2 supply currents as a function of data rate f or adum4150 channel configurations with all high speed channels running at the same speed and the low speed channels at idle. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage wavefor m applied across the insulation as well as on the materials and material interfaces . two types of insulation degradation are of primary interest: breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long - term insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working volt age, the environmental conditions , and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material g roups. lower mate rial g roup ratings are more resistant to surface tracking and therefore can provide adequate lifetime with smaller creepage . the minimum creepage for a given worki ng voltage and m aterial group is in each system level standard and is based on the total rms voltage across the isolation , pollution degree, and material g roup . the material g roup and creepage for the adum4150 isolator is presented in table 12. insulation wear out the lifetime of insulation caused by wear out is determined by its thickness, material properties , and the voltage stress applied. it is important to verify that the prod uct lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. it is the working voltage applicable to tracking that is specified in most standards. testing and modeling have shown that th e primary driver of long - term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be br oken down into broad categories , such as : dc stress , which causes very little wear out because there is no displacement current , and an ac component time varying voltage stress , which cause s wear out . rev. a | page 19 of 21
adum4150 data sheet rev. a | page 20 of 21 the ratings in certification documents are usually based on 60 hz sinusoidal stress because this stress reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in equation 2. for insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. 22 dc rmsac rms v vv ? ? (1) or 2 2 dc rms rmsac vv v ?? (2) where: v rms is the total rms working voltage. v ac rms is the time varying portion of the working voltage. v dc is the dc offset of the working voltage. calculation and use of parameters example the following is an example that frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device, see figure 18 and the following equations. figure 18. critical voltage example the working voltage across the barrier from equation 1 is 2 2 dc rmsac rms v vv ? ? 2 2 400240 ?? rms v v rms = 466 v rms this working voltage of 466 v rms is used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. the ac rms voltage can be obtained from equation 2. 2 2 dc rms rmsac vv v ?? 2 2 400466 ?? rmsac v v ac rms = 240 v rms in this case, ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for working voltage in table 16 for expected lifetime, less than a 60 hz sine wave, and it is well within the limit for a 50 year service life. note that the dc working voltage limit in table 16 is set by the creepage of the package as specified in iec 60664-1. this value may differ for specific system level standards. isolation voltag e time v ac rms v rms v dc v peak 12371-018
data sheet adum4150 rev. a | page 21 of 21 outline dimensions figure 19. 20-lead standard small outline package, with increased creepage [soic_ic] wide body (ri-20-1) dimension shown in millimeters ordering guide model 1, 2 no. of inputs, v dd1 side no. of inputs, v dd2 side maximum data rate (mhz) maximum propagation delay, 5 v (ns) isolation rating (v ac) temperature range package description package option ADUM4150ARIZ 4 2 10 24 5000 ?40c to +125c 20-lead soic_ic ri-20-1 ADUM4150ARIZ-rl 4 2 10 24 5000 ?40c to +125c 20-lead soic_ic, 13 tape and reel ri-20-1 adum4150briz 4 2 17 13 5000 ?40c to +125c 20-lead soic_ic ri-20-1 adum4150briz-rl 4 2 17 13 5000 ?40c to +125c 20-lead soic_ic, 13 tape and reel ri-20-1 eval-adum3150z evaluation board 1 z = rohs compliant part. 2 the eval-adum3150z uses a functionally equivalent device for evaluation. the pad layout on the eval-adum3150z evaluation board does not support the 20-lead soic_ic package. 11-15-2011-a 20 11 10 1 seating plane coplanarity 0.1 1.27 bsc 15.40 15.30 15.20 7.60 7.50 7.40 2.64 2.54 2.44 1.01 0.76 0.51 0.30 0.20 0.10 10.51 10.31 10.11 0.46 0.36 2.44 2.24 pin 1 mark 1.93 ref 8 0 0.32 0.23 0.71 0.50 0.31 45 0.25 bsc gage plane compliant to jedec standards ms-013 ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12371-0-3/15(a)

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